Huawei dropped a paper claiming 1.4nm-class performance without EUV, and the internet immediately declared ASML dead and US export controls useless. Austin and Vik recorded one day after Memorial Day to unpack what Huawei actually announced at ISCAS 2026 — and why the "EUV killer" headline gets the story backwards.

They walk through the tau scaling law (tau is delay, and the idea is to attack it at the system level instead of the transistor), logic folding via hybrid bonding, the Kirin 2026 that doubles transistor count without shrinking, and who can actually manufacture stacked logic. Then the other tau knobs: a unified memory bus and near-packaged optics. Along the way: BESI vs EV Group, die-to-wafer vs wafer-to-wafer bonding, and why hybrid bonding isn't export-controlled the way EUV is.

The takeaway is the opposite of the headline. Tau scaling is rational engineering under constraint, it's bullish for ASML (two DUV wafers per product, not fewer), and the moment EUV-enabled fabs stack their own advanced-node wafers, the gap widens instead of narrowing. Bullish advanced packaging, bullish EDA and multiphysics.

Chapters:
0:00 The "EUV killer" paper that broke the internet
2:28 What Huawei actually announced at ISCAS
4:00 Tau scaling: optimize delay, not transistors
8:58 The equation and the 10x AI claim
11:05 Logic folding: stacking logic on logic
17:24 Who builds it, and can hybrid bonding be banned?
24:16 Why this is bullish for ASML
29:49 The other tau knobs: memory and optics
35:18 Takeaways: packaging, EDA, multiphysics

Relevant reading:
Huawei tau scaling paper (ISCAS 2026): @TODO link
Vik's Substack write-up on the China packaging supply chain: @TODO link
Prior Semi Doped lithography deep dive: @TODO link

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Huawei's Tau Scaling Law: Is the "EUV Killer" Real?

Semi Doped

Huawei's Tau Scaling Law: Is the "EUV Killer" Real?